// followings are sample codes of "Verilog-2001 Code Book"
// Test for "Cyclone III EP3C25F324C6"

// top module for test

module shift_mul(
	input [15:0] in_p,
	input [3:0] shift_p,
	output reg [17:0] result_p,
	output reg error_p,
	input clock);
	
	reg [15:0] in;
	reg [3:0] shift;
	wire [17:0] result;
	wire error;
	
	always@(posedge clock) begin
		in <= in_p;
		shift <= shift_p;
		result_p <= result;
		error_p <= error;
	end
//	unsigned_shift_left_1 u1(.in(in), .result(result[16:0]));
		assign error = 1'b0; assign result[17] = 1'b0;
//	unsigned_shift_left_1_clip u1(.in(in), .result(result[15:0]),
		.error(error)); assign result[17:16] = 2'b0;
	signed_shift_left_variable_clip u1(.in(in), .shift(shift), .result(result[15:0]),
		.error(error)); assign result[17:16] = 2'b0;
endmodule	

// unsigned shift

module unsigned_shift_left_1(
	input [15:0] in,
	output [16:0] result);
	
	assign result = {in, 1'b0}; 
endmodule

module unsigned_shift_left_1_clip(
	input [15:0] in,
	output [15:0] result,
	output error);
	
	wire [16:0] work = {in, 1'b0}; 
	assign error = work[16];
	assign result = error ? 16'hFFFF : work[15:0];
endmodule

module unsigned_shift_right_1(
	input [15:0] in,
	output [15:0] result);

	assign result = {1'b0, in[15:1]}; 
endmodule

module unsigned_shift_right_variable(
	input [15:0] in,
	input [3:0] shift,
	output [15:0] result);

	wire [15:0] work0 = shift[0] ? {1'b0, in[15:1]} : in;
	wire [15:0] work1 = shift[1] ? {2'b0, work0[15:2]} : work0;
	wire [15:0] work2 = shift[2] ? {4'b0, work1[15:4]} : work1;
	assign result = shift[3] ? {8'b0, work2[15:8]} : work2;
endmodule

// signed shift

module signed_shift_right_1(
	input [15:0] in,
	output [15:0] result);

	assign result = {in[15], in[15:1]}; 
endmodule

module signed_shift_left_1_clip(
	input [15:0] in,
	output [15:0] result,
	output error);

	assign error = ^in[15:14];
	assign result = error ? (in[15] ? 16'h8000 : 16'h7FFF)
						  : {in[14:0], 1'b0}; 
endmodule

module signed_shift_right_variable(
	input [15:0] in,
	input [3:0] shift,
	output [15:0] result);

	wire [15:0] work0 = shift[0] ? {in[15], in[15:1]} : in;
	wire [15:0] work1 = shift[1] ? {{2{work0[15]}}, work0[15:2]} : work0;
	wire [15:0] work2 = shift[2] ? {{4{work1[15]}}, work1[15:4]} : work1;
	assign result = shift[3] ? {{8{work2[15]}}, work2[15:8]} : work2;
endmodule

module signed_shift_left_variable_clip(
	input [15:0] in,
	input [3:0] shift,
	output [15:0] result,
	output error);

	wire [16:0] work0 = shift[0] ? {in, 1'b0} : {1'b0, in};
	wire [18:0] work1 = shift[1] ? {work0, 2'b0} : {2'b0, work0};
	wire [22:0] work2 = shift[2] ? {work1, 4'b0} : {4'b0, work1};
	wire [30:0] work3 = shift[3] ? {work2, 8'b0} : {8'b0, work2};
	assign error = ~&work3[30:15] & |work3[30:15];
	assign result = error ? (work3[30] ? 16'h8000 : 16'h7FFF)
						  : work3[15:0];
endmodule

// multiplier

module unsigned_mul_5(
	input [15:0] in,
	output [17:0] result);

	assign result = {in, 2'b0} + {2'b0, in}; 
endmodule